This relates generally to integrated circuits, and more particularly, to integrated circuits with clock signal distribution circuitry.
Integrated circuit often include clock generation circuitry such as phase-locked loops (PLLs). A phase-locked loop typically has an input that receives a reference clock signal and outputs at which multiple clocks signals are provided. The multiple clocks signals generated at the outputs of the phase-locked loop can exhibit clock rates that are integer multiples of the clock rate of the input reference clock signal.
The clock signals generated using the phase-locked loop can be distributed to different regions on an integrated circuit on which the phase-locked loop is formed using clock distribution circuitry—sometimes referred to as the clock network. The clock network can include many branches of series-connected clock buffers (i.e., clock buffers connected serially in a chain) through which the clock signals are passed. Because the clock signals propagating through the clock network constantly toggle between logic low and logic high levels, the clock network is a significant contributor to the total dynamic power loss of the integrated circuit. Typically, the clock distribution network can consume up to 60% of the total chip power. This percentage is exacerbated as semiconductor technology scales toward higher density designs and as the need for higher performance devices continues to push operating frequencies higher.
It is within this context that the embodiments described herein arise.